时序Sign-off的革命

The Revolution of Timing Sign-off

  演讲人：

董森华

产品与技术支持总监

北京华大九天软件有限公司

Dong Senhua

Senior Director of Product and Application

                   Huada Empyrean Software Co., Ltd.

演讲人简历：

董森华，清华大学微电子所硕士毕业。多年来专注于SoC数字后端优化方案研究，2004年起带领团队开始时钟、时序、功耗优化方案——ICExplorer的设计研发，并将产品打造成为全球信赖的高端产品。

Dong Senhua, Master, graduated from Tsinghua University. The R&D director of HUADA Empyrean Software Company. In the past years, Senhua leads the EDA product development, some of products, such as clock analysis, timing and power optimization, have been adopted by many world-class IC companies as the golden design flow.

报告摘要：

先进工艺的process variation呈现明显的非正态分布，打破了传统STA时序sign-off方案的理论假设，特别是IoT的超低电压情况下，时序精度的问题尤为突出。表现为芯片的实际工作状态和STA sign-off的结果呈现明显差异，性能差异大，良率变低，设计周期急剧拉长，工程师努力使用更多的corner，更大的margin，花费更长的时间，但效果只是让STA看起来没有时序问题，却无法保证芯片真正工作。这一切都要求我们重新设计更精确的时序sign-off方案。

Timing changes below 16nm, process variation becomes very Non-Gaussian, even worse for IoT. The traditional STA sign-off no longer works, silicon works very different with STA sign-off, different performance, bad yield, designer works much harder for STA sign-off, too many corners used for STA sign-off, much more margin killed design PPA, many iterations and time-consuming for timing closure, but still make the silicon success. For better design PPA, yield and TAT, need more accurate silicon sign-off solution.